When data communication is performed between apparatuses, since a receiver apparatus and a transmitter apparatus have asynchronous clocks and, in addition, different clock frequencies due to different operating environments (e.g., power supply noise, temperature, etc.), the receiver apparatus needs to reproduce clocks based on received data. This process is generally called timing recovery, data clock recovery or the like. In general timing recovery, clocks are generated in a receiver, a phase difference between the clocks and received data is detected, and the frequency or phase of the clocks is adjusted, depending on the detected phase difference, which steps are repeatedly performed.
FIG. 24 shows a general phase difference detecting means. A data detecting means 161 and a clock detecting means 162 are flip-flops, in which their data pins are fixed to the “H level”, and a data signal and a clock signal are input to their clock pins, respectively, and a reset signal output from a determination means 163 is input to their reset pins. When the data signal goes to the “H level”, the output of the data detecting means 161 goes to the “H level” and is then output as an UP signal. Similarly, when the clock signal goes to the “H level”, the output of the clock detecting means 162 goes to the “H level” and is then output as a DOWN signal. The determination means 163 monitors the output of the data detecting means 161 and the output of the clock detecting means 162, and when both of the outputs go to the “H level”, outputs a reset signal. In other words, the output of the data detecting means 161 and the output of the clock detecting means 162, when both go to the “H level”, are reset to the “L level”. Therefore, when the data signal arrives earlier than the clock signal, the “UP signal” is output for the same period as the phase difference. In the opposite situation, the “DOWN signal” is output for the same period as the phase difference. Thereby, it is possible to detect how much the phase of the clock signal is advanced or delayed from the data signal.
The phase difference detection by such a method can be achieved by a simple circuit. However, as the data rate is increased, the pulse width of the UP signal and the DOWN signal decreases, so that full swing cannot be performed, and therefore, it becomes more difficult to correctly detect a phase difference. To solve such a problem, methods of determining a phase using the result of oversampling of received data are disclosed in U.S. Pat. No. 5,905,769 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2004-180188 (Patent Document 2).
Patent Document 1 discloses a phase comparator that latches four bits of received data using a clock signal having twelve phases. Specifically, a phase comparison process in which three-times oversampling is executed with respect to one bit of received data is performed for four bits in parallel. Three-times oversampling means that received data having a one-bit width of “T” is held at periods of “T/3” three times. Thus, based on a result from latching one bit of received data a plurality of times at different timings, a phase relationship between received data and a clock signal can be found. For example, when three-times oversampling is executed near a time when received data is transitioned in a manner that “0→1→0→ . . . ” (near a data transition point), then if the phase relationship between received data and a clock signal is in a desired state (ideal phase relationship), “(000)(111)(000) . . . ” is obtained. However, when the latched result is “(001)(110)(001) . . . ”, it can be determined that the phase of the clock signal is delayed from the received data. Conversely, when the latched result is “(100)(011)(100) . . . ”, it can be determined the phase of the clock signal is advanced from the received data.
Patent Document 2 discloses a phase detecting circuit in which an effect equivalent to oversampling is obtained by delaying received data instead of using multi-phase clocks. FIG. 25 shows a configuration of a phase comparator disclosed in Patent Document 2. Here, two delay elements 171 are used to delay received data in two steps, and two outputs of the delay elements 171 and non-delayed data (i.e., three pieces of data) are latched in synchronization with a clock signal from a frequency divider 172. As in Patent Document 1, the latched result is 3-bit information, such as (001), and based on the result, a phase delay signal or a phase advance signal is output.
Here, the phase comparator of Patent Document 2, when a delay amount of each delay element 171 is “T/3”, performs an operation similar to that of the phase comparator disclosed in Patent Document 1. However, when the delay amount is “less than T/3”, a “dead zone” occurs in which phase determination is not performed. For the sake of simplicity, the SETUP/HOLD time of a flip-flop is assumed to be “0” and the delay amount of the delay element 171 is assumed to be “D”. In this case, a phase delay signal or a phase advance signal is output only when a data transition point occurs during a period from a rising edge of the clock signal to a point in time that is a period corresponding to a delay amount of 2D before the rising edge of the clock signal. In other words, when a data transition point occurs during a period from a “rising edge of a clock signal one cycle before” to a “point in time that is a period corresponding to a delay amount of 2D before the next rising edge”, phase determination is not performed. Thus, this period is a dead zone.
In the phase comparators shown in Patent Document 1 and FIG. 25 (Patent Document 2), only a phase relationship between received data and a clock signal is determined, so that even when the communication speed of data is increased, a problem that a pulse indicating the phase difference is distorted does not arise, for example. Also, since the output result is in a digital form, pipelined or parallel processing can be easily performed, resulting in a circuit configuration suitable for high-speed communication.    Patent Document 1: U.S. Pat. No. 5,905,769    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2004-180188